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data sheet tle 6232 gp v2.1 page 2007 - 04 - 20 1 smart six channel low - side switch features product summary short circuit protection up to 24 v over - temperature protection over - voltage protection 16 bit serial data input and diagnostic output (2 bit/ch. acc. spi prot o col) direct pa rallel control of all six cha n- nels for pwm applications general fault flag low quiescent current compatible with 3v micro controllers e lectr o static d ischarge (esd) prote c tion parallel inputs high or low active programmable green product (rohs compliant) aec qualified application c compatible power switch for 12 v and 24v applications switch for automotive and industrial system solenoids, relays and resistive loads robotic controls general description six chan nel low - side switch in smart power technology (spt) with a s erial p eripheral i nterface (spi) and six open drain dmos output stages. the tle 6232 gp is protected by embedded protection fun c- tions and d e signed for automotive and industrial applications. the o utput stages are controlled via an spi interface. additionally all six channels can be controlled direct in para l lel for pwm applications. therefore the tle 6232 gp is particularly suitable for engine management and powe r train systems. block diagram supply voltage v s 4.5 ? 5.5 v drain source clamping voltage v ds(az)typ. 53 v on resistance r on1 - 4 0.25 w r o n 5,6 0.45 w output current (channel 1 - 4) i d(nom) 2 a (channel 5,6) i d(nom) 1 a p g - dso 36 - 26 reset fault cs output stage output control buffer serial interface spi logic sclk si 6 6 gnd vs so 1 6 in1 out1 out6 prg v bb vs as ch. 1 16 gnd protection functions as ch. 1 as ch. 1 as ch. 1 in6 as ch. 1
data sheet tle 6232 gp v2.1 page 2007 - 04 - 20 2 detailed block diagram fault reset channel 2 channel 3 channel 4 channel 5 channel 6 sclk vs in1 out1 out2 out3 out4 out5 out6 spi interface 16 bit normal function scb/overload/ot open load short to ground prg vs gnd output stage si so gnd in3 as ch.1 in4 as ch.1 in2 as ch.1 in5 as ch.1 in6 as ch.1 16 6 output control buffer 6 cs
data sheet tle 6232 gp v2.1 page 2007 - 04 - 20 3 pin description pin configuration (top view) pin symbol function 1 gnd ground 2 nc not connected 3 out5 power output channel 5 4 nc not connected 5 out1 power output channel 1 6 in5 input channel 5 7 in1 input channel 1 8 vs supply voltage 9 reset reset 10 cs slave select 11 prg program (inputs high or low - active) 12 in2 input channel 2 13 in6 input channel 6 14 out2 power output channel 2 15 nc not connected 16 out6 power output channel 6 17 nc not connected 18 gnd ground 19 gn d ground 20 nc not connected 21 nc not connected 22 nc not connected 23 out3 power output channel 3 24 nc not connected 25 in3 input channel 3 26 fault general fault flag 27 so serial data output 28 sclk serial clock 29 si serial d ata input 30 in4 input channel 4 31 nc not connected 32 out4 power output channel 4 33 nc not connected 34 nc not connected 35 nc not connected 36 gnd ground heat slug internally connected to ground pins gnd 1 36 gnd nc 2 35 nc out5 3 34 nc nc 4 33 nc out1 5 32 out4 in5 6 31 nc in1 7 30 in4 vs 8 29 si reset 9 28 sclk cs 10 27 so prg 11 26 fault in2 12 25 in3 in6 13 24 nc out2 14 23 out3 nc 15 22 nc out6 16 21 nc nc 17 20 nc gnd 18 19 gnd power so 36
data sheet tle 6232 gp v2.1 page 2007 - 04 - 20 4 maximum ratings for t j = ? 40c to 150c parameter symbol values unit supply voltage v s - 0.3 ... +7 v continuous drain source voltage (out1...out8) v ds 45 v input voltage, all inputs and data lines v in - 0.3 ... + 7 v operating temperature range storage temperature range t j t stg - 40 ... + 150 - 55 ... + 150 c output current per channel (see el. characteri s tics) i d(lim) i d(lim) min a single pulse inductive energy ( internal clamping) t j =125c, ch1 - 4: 3a linear decreasing ch5,6: 1,5a linear decreasing e 40 20 mj output current per chan nel @ t a = 25c (all 6 channels on; mounted on pcb ) 1 ) i d 1 - 4 i d 5,6 1.1 0.55 a power dissipation (mounted on pcb) @ t a = 25c p tot 3.3 w electrostatic discharge voltage (human body model) according to mil std 883d, method 3015.7 and eos/esd assn. stand ard s5.1 - 1993 v esd 2000 v din humidity category, din 40 040 e iec climatic category, din iec 68 - 1 40/150/56 thermal resistance junction ? case (die soldered on the frame) junction - ambient @ min. footprint junction - ambient @ 6 cm 2 cooling area with heat pipes r thjc r thja 2 50 38 k/w 1 ) output current rating so long as maximum junction temperature is not exceeded. at t a = 125 c the output cu r rent h as to be calculated using r thja according mounting conditions. pcb with heat pipes, backside 6 cm 2 cooling area minimum footprint
data sheet tle 6232 gp v2.1 page 2007 - 04 - 20 5 electrical characteristics parameter and conditions symbol values unit v s = 4.5 to 5.5 v ; t j = - 40 c to + 150 c ; reset = h (unles s otherwise specified) min typ max 1 . power supply, reset supply voltage 2 v s 4.5 -- 5.5 v supply current i s -- -- 10 ma supply current in standby mode (reset = l) i s(stdy) -- -- 10 a minimum reset duration t r e set,min 1 -- -- s 2 . power outputs on resistance v s = 5 v ; i d = 1 a t j = 25c channel 1 - 4 t j = 150c r ds(on) -- -- 0.25 -- 0.28 0.5 w on resistance v s = 5 v ; i d = 500 ma t j = 25c channel 5,6 t j = 150c r ds(on) -- -- 0.45 -- 0.55 1 w output clamping voltage output off v ds(az) 45 53 60 v cu rrent limit channel 1 - 4 current limit channel 5,6 i d(lim) 1 - 4 i d(lim) 5,6 3 1.5 4 2 6 3 a output leakage current v reset = l i d(lkg) -- -- 10 a turn - on time ch 1 - 4 i d = 2 a, resistive load ch 5,6 i d = 1 a, resi s tive load t on -- 5 10 s turn - off t ime ch 1 - 4 i d = 2 a, resistive load ch 5,6 i d = 1 a, resi s tive load t off -- 5 10 s switch - on slew rate (resistive load) s on 1 4 20 v/s switch - off slew rate (resistive load) s on 1 4 20 v/s 3 . digital inputs input low voltage v inl - 0.3 -- 1.0 v input high voltage v inh 2.0 -- -- v input voltage hysteresis v inhys 100 200 400 mv input pull down/up current (in1 ... in6) i in(1..6) 10 20 50 a input pull up current (reset) i in(res) 10 20 50 a input pull down current (prg) i in(prg) 10 20 50 a input pull up current ( cs , si, sclk) i in(si,sclk) 10 20 50 a 4 . digital outputs (so, fault ) so high state output voltage i soh = - 2 ma v soh v s - 1 -- -- v so low state output voltage i sol = 2 ma v sol -- -- 0.4 v output tri - state leakage current cs = h, 0 v so v s i solkg - 10 0 10 a fault output low voltage i fault = 2 ma v faultl -- -- 0.4 v 2 for v s < 4.5v the power stages are switched according the input signals and data bits or are definitely switched off. this under - voltage reset gets active at v s = 3v (typ. value) and is speci fied by design.
data sheet tle 6232 gp v2.1 page 2007 - 04 - 20 6 electrical characteristics cont. parameter and conditions symbol values unit v s = 4.5 to 5.5 v ; t j = - 40 c to + 150 c ; reset = h (unless otherwise specified) min typ max 5 . diagnostic functions open load detection voltage v ds(ol) 0.52* v s 0.6* v s 0.68* v s v short to ground detection voltage v ds(shg) 0.32 * v s 0.4 * v s 0.48 * v s v diagnostic cu rrent (incl. leakage) u outi,j = 14v u outi,j = 0v i outi,j - i outi,j 325 50 580 130 980 250 a a current limitation; overload threshold current i d(lim) 1 - 4 i d(lim) 5,6 3 1.5 4 2 6 3 a a over - temperature shutdown threshold hysteresis t th(sd) t hys 170 5 -- 10 200 20 c k fault delay time t d(fault) 60 120 240 s 6 . spi - timing serial clock frequency (@ c so 50pf) f sck dc -- 5 mhz serial clock period (1/fclk) t p(sck) 200 -- -- ns serial clock high time t sckh 50 -- -- ns serial clock low time t sckl 100 -- -- ns enable lead time (falling edge of cs to rising edge of clk ) t lead 100 -- -- ns enable lag time (falling edge of clk to rising edge of cs ) t lag 150 --- -- ns data setup time (required time si to falling of clk) t su 20 -- -- ns data hold time (falling edge of clk to si) t h 20 -- -- ns disable time t dis -- -- 100 ns transfer delay time 3 ( cs high time between two accesses) t dt 150 -- -- ns data valid time 4 c l = 50 pf c l = 100 pf c l = 150 pf t valid -- -- -- -- -- -- 10 0 120 150 n s ns ns 3 this time is necessary between two write accesses. to get the correct diagnostic information, the transfer delay time has to be extended to the maximum fault delay time t d(fault)max = 200s. 4 this parameter will not be tested but specif ied by design
data sheet tle 6232 gp v2.1 page 2007 - 04 - 20 7 description of the power stages 4 low side power switches for nominal currents up to 3a (power stages out1 to out4). co n trol is possible by input pins or via spi. for t j = 150c the on - resistance o f the power switches is below 500m w . 2 low side power switches for nominal currents up to 1.5a (power stages out5 and out6). control is possible by input pins or via spi. for t j = 150c the on - resistance of the power switches is below 1 w . in order to inc rease the switching current or to reduce the power dissipation parallel conne c tion of power stages is possible. each of the 6 output stages is equipped with its own zener clamp, which limits the output vol t- age to a maximum of 60v. the outputs are provide d with a current limitation set to a minimum of 1.5a resp. 3a. each power stage is equipped with an own temperature sensor. each output is protected by embedded protection functions 5 ) . in case of overload or short - circuit to u batt the current is internall y limited and the corresponding bit combination is set (early warning). if this operation leads to an over - temperature condition, a second protection level (about 170c) will change the output into a low duty cycle pwm (selective thermal shut - down with res tart) to prevent critical chip te m peratures. the following faults can be detected (individually for each output): - short to ubatt: (scb/overload) can be detected when switches are on state - short to ground: (scg) can be detected when switches are off state - open load: (ol) can be detected when switches are off state - over - temperature : (ot) will only be detected when switches are on state the fault conditions scb, scg and ol will not be stored until an integrated filtering time is e x- pired (please note for pwm application). if, at one output, several errors occur in a s e quence, always the last detected error will be stored (with filtering time). all fault conditions are encoded in two bits per switch and are stored in the corresponding spi registers. additio nally there are two central diagnostic bits: one especially for over - temperature (latched result of an or - operation out of the 6 signals of the temperature sensor) and one for fault occu r rence at any output. a fault that has been detecte d and stored in the fault register must not be replaced by o.k. - state (11) unless it is read out by the rd_diag command sent by the micr o controller or an internal or external reset has been applied. i.e. the fault register will be cleared only by the rd_di ag command. prg - program pin. prg = high ( v s ): parallel inputs channel 1 to 6 are high active prg = low (gnd): parallel inputs channel 1 to 6 are low active. if the parallel input pins are not connected (independent of high or low activity) , channels 1 to 6 are switched off. prg pin itself is internally pulled down when it is not connected. 5 ) the integrated protection functions prevent device destruction under fault conditions and may not be used in normal operation or permanently.
data sheet tle 6232 gp v2.1 page 2007 - 04 - 20 8 the effect of the integrated under - voltage detection is similar to the effect of an external reset at pin reset (except low current consumption): - locks all po wer switches regardless of their input signals - clears the fault registers - resets spi control register parallel connection of power stages the power stages which are connected in parallel have to be switched on and off simultan e- ously. in case of ove rload the ground current and the power dissipation are increasing. the applic a- tion has to take into account that all maximum ratings are observed (e.g. operating temper a ture t j and total ground current i gnd , see maximal ratings). the maximum current limit ation value (or overload detection threshold) of the parallel co n- nected power stages is the summation of the corresponding maximum values of the power stages (iout (lim)x + i out(lim)y + ....). max. nominal current max. clamping energy on resistance 2 po wer stages of the same type (see note 1) (i max,outx +i max,outy ) x 0.9 0.8 x (ex + ey) y outx on xr , , 5 . 0 3 power stages of the same type (see note 1,2) (i max,outx +i max,outy + i max,outz ) x 0.8 0.7 x (ex + ey + ez) z y outx on xr , , , 34 . 0 2 power stages with the same clamping voltage, but different nominal current (see n o te 3) (i max,outx +i max,outy ) x 0.8 min (eclpx , eclpy) outy on outx on outy on outx on r r xr r , , , , + note 1: power stages of the same type have the same nominal current note 2: only for 3a power stages note 3: parallel conne ction of power stage type 3a/53 v with type 1.5a/53v spi interface the serial spi interface makes possible communication between tle6232 and the microco n- tro l ler. tle 6232 gp always works in slave mode whereas the mi cro controller provides the master function. the maximum baud rate is 5mbaud. applying a chip select signal at cs and setting bit 7 and bit 6 of the instruction byte to ?1? and ?0? tle 6232 gp is selected by the spi master. si is the data input (signal in) , so the data output (signal out). via sclk (serial clock input) the spi clock is given by the master.
data sheet tle 6232 gp v2.1 page 2007 - 04 - 20 9 spi signal description cs - chip select. the system microcontroller selects the tle 6232 gp by means of the cs pin . whenever the pin is in a logic low state, data can be transferred from the c and vice versa. cs high to low transition: - diagnostic status information is transferred from the power outputs into the shift register. - serial input data can be clocked in from then on - so changes from high impedance state to logic high or low state corresponding to the so bits cs low to high transition: - transfer of si bits from shift re gister into output buffers - reset of diagnosis register to avoid any false clocking the serial clock input pin sclk should be logic low state during high to low transition of cs . when cs i s in a logic high state, any signals at the sclk and si pins are ignored and so is forced into a high impedance state. sclk - serial clock. the system clock pin clocks the internal shift register of the tle 6232 gp. the serial input (si) accepts data into the input shift register on the falling edge of sclk while the serial output (so) shifts diagnostic information out of the shift register on the rising edge of serial clock. it is essential that the sclk pin is in a logic low state whenever chip select cs makes any transition. the number of clock pulses will be counted during a chip select cycle. the received data will only be accepted, if exactly 16 clock pulses were counted during cs is active. si - serial input. seri al data bits are shifted in at this pin, the most significant bit first. si inform a- tion is read in on the falling edge of sclk. input data is latched in the shift register and then transferred to the control buffer of the output stages. the input data con sists of two bytes - a "control byte? followed by a "data byte". the control byte contains the information as to whether the data byte will be accepted or ignored (see d i- agnostics section). the data byte contains the input information for the six channels. a logic high level at this pin (within the data byte) will switch on the power switch, provided that the co r- responding pa r allel input is also switched on ( and - operation for channel 1 to 6 ). so - serial output. diagnostic data bits are shifted out serial ly at this pin, the most significant bit first. so is in a high impedance state until the cs pin goes to a logic low state. new dia g- nostic data will appear at the so pin following the rising edge of sclk. reset - reset pin . if the reset pin is in a logic low state, it clears the spi shift register and switches all outputs off. an internal pull - up structure is provided on chip. in case of inactive chip select signal (high) or bit 7 and bit 6 of the instruction byte differing from1? and ?0? the data output so remains into tri - state .
data sheet tle 6232 gp v2.1 page 2007 - 04 - 20 10 spi interface spi communication a spi communication starts with a spi instruction (si control word) sent from the controller to tle 6232 gp. simultaneously the device sends the first so byt e back to the c. during a writing cycle the controller sends the data after the spi instruction, beginning with the msb. during a reading cycle, after having received the spi instruction, tle 6232 gp sends the corresponding data to the controller, also st arting with the msb. the spi interface consists of three register: - mux_reg: 8 - bit (1 byte) length for parallel operation mode (in1 ... in6 enabled or not) - scon_reg: 8 - bit (1 byte) length for serial control of the outputs (serial data bits) cs sclk spi control: so sck si cs power stages 1.. . 6 state machine shift register power stages 1...6 mux_reg scon_reg clock counter control bits parity generator power stages 1. ..6 dia_reg
data sheet tle 6232 gp v2.1 page 2007 - 04 - 20 11 - diag_reg: 16 - bit (2 byte) length. contains the diagnostic information (2 bits per cha n- nel), a common over - temperature bit and a common fault bit. registers mux_reg and scon_reg are writeable as well as readable from the microcontro l- ler. the diag_reg can only be re ad from the c. this leads to five different control bytes which are recognized by the ic. the following table shows the different modes. msb lsb msb lsb wr_scon si: so: h l l h h l x x z z f ot dia6 dia5 d6 d5 d4 d3 d2 d1 x x dia4 dia3 dia2 dia1 write to scon r e gister. rd_scon si: so: h l l h l h x x z z f ot dia6 dia5 x x x x x x x x scon6 .. . scon1 h h read scon regi s ter wr_mux si: so: h l h l h l x x z z f ot dia6 dia5 m6 m5 m4 m3 m2 m1 x x dia4 dia3 dia2 dia1 write to mux r e gister. rd_mux si: so: h l h l l h x x z z f ot dia6 dia5 x x x x x x x x mux6 . . mux1 h h read mux register rd_diag si: so h l l l l l x x z z f ot dia6 dia5 x x x x x x x x dia4 dia3 dia2 dia1 read diag register si control byte si data byte note: ?x? means ?don?t care?, because data will be ignored ?dx? represents the serial data bit s, either being h (= off) or l (= on) ?mx? enables parallel control of channel x h (=parallel) or l (=serial) ?z? means tri - state ?f? is the common fault flag ?ot? is the common over - temperature flag ?diax? is the 2 bit diagnosis information per channel all other possible control bytes will lead to an ignorance of the data bits, but the full diagnosis information (like rd_diag command) is provided at the so line. a reset of all fault registers (and ot bit) the will only be done if the rd_diag command was clocked in. characteristics of the spi interface if the slave select signal at cs is high or bit 7 and bit 6 of the instruction byte differ from ?1? and ?0?, the state machine is set on default condition, i.e. the state machine expects an instru c- tion. if the 5v - reset (reset) is active, the spi output so is switched into tri - state . in order to increase the possible number of spi participants on one and the same cs signal, bits 7 and 6 of the instruction byte are fixed as shown above. while receiving the first two bits of the instruction byte the data output so has to be in tri - state . after having received the first two bits tle6232 has to decide if it is addressed (bit 7 = high, bit 6 = low). in this case the remai n- ing 6 bits of the instruction byte and the data byte are accepted and the diagnostic fee d back respectively the data byte content (mux, scon) is sent to the microcontroller. otherwise i n- struction and data bits are rejected and so remains in tri - state . on a reading access the bit pattern of the d ata byte at the spi input si will be ignored. the first so byte sent out simultaneously by the tle 6232 gp always contains the common fault bit, the over - temperature bit and the diagnostic information of channels 6 and 5 (2 bits each). depen d- ing on the si control byte, the second so byte contains the requested information.
data sheet tle 6232 gp v2.1 page 2007 - 04 - 20 12 - read back of scon_reg (scon bits 6 to 1 and two high bits) - read back of mux_reg (mux information for channel 6 to 1 and two high bits) - diagnostic information of channel 4 to 1 (2 bi ts per channel) on a writing access always the full diagnostic information of the 6 channels (2 bit per channel) and the over - temperature and common fault bit is performed. invalid instruction/access: an instruction is invalid, if the following condition is fulfilled: - an unused instruction code is detected (see tables with spi instructions). if an invalid instruction is detected, a writing access on a register of tle6232 gp is not allow - wed. in addition an access is invalid if the number of spi clock p ulses counted during active cs differs from exactly 16 clock pulses (fa l ling edges are counted). - on a writing access the received data is only taken over into the internal registers and - the fault register is only cleared by the rd_diag command, if exa ctly 16 spi clock pulses were counted while cs active. writing access / 8 bit + 8 bit resp. spi instruction ss si so msb data/8 bit ss dia4 dia3 dia2 dia1 msb msb z z f ot dia6 dia5 1 0 - - - - - - spi instruction si so msb xxxx xxxx msb msb z z ot dia6 dia5 f 1 0 - - - - - - reading access / 8 bit + 8 bit data/8 bit
data sheet tle 6232 gp v2.1 page 2007 - 04 - 20 13 serial/parallel control of the power stages 1...6 (spi - instructions : wr_mux, rd_mux, wr_scon, rd_scon) the following table shows the truth table for the control of the power stages 1...6. the reg ister mux_reg prescribes parallel or serial control of the power stages. the register scon_reg prescribes the state of the power stage in case of serial control. rst prg inx muxx sconx output outx of power stage x, x = 1..6 0 x x x x outx off 1 x x 0 0 serial control: outx on 1 x x 0 1 serial control: outx off 1 0 0 1 x parallel co n trol: outx on 1 0 1 1 x parallel co n trol: outx off 1 1 0 1 x parallel co n trol: outx off 1 1 1 1 x parallel co n trol: outx on note: serial data bits are low active. parallel inputs are high or low active depending on the prg pin. description of the spi registers register: mux_reg 7 6 5 4 3 2 1 0 mux6 mux5 mux4 mux3 mux2 mux1 1 1 state of reset: ffh access by controller: read/writ e bit name descri p tion 7 mux6 serial or parallel control of power stage 6 6 mux5 serial or parallel control of power stage 5 5 mux4 serial or parallel control of power stage 4 4 mux3 serial or parallel control of power stage 3 3 mux2 serial or parallel control of power stage 2 2 mux1 serial or parallel control of power stage 1 1 - 0 no function: high on reading register: scon_reg 7 6 5 4 3 2 1 0 scon6 scon5 scon4 scon3 scon2 scon1 1 1 state of reset: ffh access by controller: read/write bit name descri p tion 7 scon6 state of serial control of power stage 6 6 scon5 state of serial control of power stage 5 5 scon4 state of serial control of power stage 4 4 scon3 state of serial cont rol of power stage 3 3 scon2 state of serial control of power stage 2 2 scon1 state of serial control of power stage 1 1 - 0 no function: high on reading
data sheet tle 6232 gp v2.1 page 2007 - 04 - 20 14 diagnostics/encoding of failures description of the spi registers (spi instructions: rd_dia g) register: diag_reg1 7 6 5 4 3 2 1 0 st7 st6 st5 st4 st3 st2 st1 st0 state of reset: ffh access by controller: read only bit name d e scription 7 - 6 dia4 dia g nostic bits of power stage 4 5 - 4 dia3 dia g nostic bits of power stage 3 3 - 2 dia2 dia g nostic bits of power stage 2 1 - 0 dia1 dia g nostic bits of power stage 1 note: this byte is always clocked out (second so - byte), except the si control words says: rd_scon or rd_mux. but: the content of the faul t register will only be deleted if the control command ?rd_diag? was clocked in and 16 clock pulses were counted. register: dia_reg2 7 6 5 4 3 2 1 0 z z f ot st11 st10 st9 st8 state of reset: ffh access by controller: read onl y bit name d e scription 7 - 6 z bit 7 and 6 are always tri - state 5 f co m mon error flag 4 ot common over - t e mperature flag 3 - 2 dia6 dia g nostic bits of power stage 6 1 - 0 dia5 dia g nostic bits of power stage 5 encoding of the diagnostic ( status ) bits of the power stages st(2*x - 1) st(2*x - 2) state of power stage x x = 1..6 1 1 power stage o.k. 1 0 overload, short circuit to battery (scb) or over - t e mperature (ot) 0 1 open load (ol) 0 0 short circuit to gr ound (scg) note: dia_reg2 is always clocked out as first byte f, ot bit = 1: no fault f, ot bit = 0: fault, over - temperature the over - temperature bit is the latched result of an or - operation out of the 6 signals of the te m perature sensor) the general fa ult bit shows the fault occurrence at any of the outputs. reset of the diagnostic information
data sheet tle 6232 gp v2.1 page 2007 - 04 - 20 15 the diagnostic information will only be reset after the rd_diag command on the rising edge of slave select or a reset signal is applied (reset = low).
data sheet tle 6232 gp v2.1 page 2007 - 04 - 20 16 timing d iagrams figure 2: serial interface figure 3: input timing diagram figure 4: so valid time waveforms enable and disable time waveforms c o n t r o l byte 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cs sclk si so msb lsb t lead t sckh 0.2v s t lag t h t fsi t sckl 0.2 v s t su t rsi 0.7v s 0.2v s cs sclk si 0.7v s 0.7vs t dt t valid sclk cs so t dis 0.2 v s so 0.7 v s 0.7 v s 0.2 v s so 0.7 v s 0.2 v s
data sheet tle 6232 gp v2.1 page 2007 - 04 - 20 17 figure 5: power outputs timing is valid for resistive load with parallel and serial control. rising edge of chip select initiates the switching a pplication circuits t t t on t off 80% v ds v in 20% out1 out2 out6 tle 6232 gp si so clk cs vs v s = 5v reset gnd v bb clk mtsr mrst p xy c e.g. c167 in1 in6 prg fault 10k c
data sheet tle 6232 gp v2.1 page 2007 - 04 - 20 18 parallel spi configuration engine management application tle 6232 gp in combination with tle 6240 gp (16 - fold switch) for relays and general pu r pose loads and tle 6220 gp (quad switch) to drive the injector valves. this arrangement cov ers the numerous loads to be driven in a modern engine management/powertrain system. from 26 channels in sum 18 can be controlled direct in parallel for pwm applications. 4 si clk so 4 si clk so cs cs mtsr mrst clk p x.y p x.1-6 p x.y p x.1-4 c c167 4 pwm channels 6 pwm channels cs injector 1 injector 2 injector 3 injector 4 tle 6220 gp quad tle 6232 gp hex 8 si clk so cs 8 pwm channels tle 6240 gp 16-fold p x.y p x.1-8
data sheet tle 6232 gp v2.1 page 2007 - 04 - 20 19 package and ordering code ( all dimensions in mm) p g - ds o 36 - 26 ordering code tle 6232 gp q67007a9397a702 green product (rohs compliant) to meet the world - wide customer requirements for environmentally friendly products and to be compl i ant with government regulations the device is a vailable as a green product. green products are rohs - compliant (i.e pb - free finish on leads and suitable for pb - free soldering according to ipc/jedec j - std - 020).
data sheet tle 6232 gp v2.1 page 2007 - 04 - 20 20 revision hi story version date changes v2.0 - > v2.1 ordering code / q - nr. removed v2.0 - > v2.1 05.04.2007 layout changes, correct gree n package name implemented p - dso - 36 - 12 pg - dso - 36 - 26 v1.2 - > v2.0 05.03.2007 green date sheet version created v2.0 05.03.2007 changes to green product version: - aec, rohs logo and feature list content added - package name p - dso - > pg - dso - change history added - disclaimer re - newed v1.2 08. oct. 2003 initial version of ?grey? product
data sheet tle 6232 gp v2.1 page 2007 - 04 - 20 21 edition 2007 - 04 - 17 published by infineon technologies ag 81726 munich, germany ? 5/4/07 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or chara c- teristics. with respect to any examples or hints given herein, any typical values stated herein and/or any info r- mation regarding the appli cation of the device, infineon technologies hereby disclaims any and all warranties and liabil i ties of any kind, including without limitation, warranties of non - infringement of intellectual property rights of any third party. information for further inform ation on technology, delivery terms and conditions and prices, please contact the nearest i n fineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life - support devices or systems only with the express wri t- ten approval of infineon technologies, if a failure of such components can reasonab ly be expected to cause the fai l ure of that life - support device or system or to affect the safety or effectiveness of that device or system. life su p port devices or systems are intended to be implanted in the human body or to support and/or maintain and su stain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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